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Features of Codes Compressing by Multiplier Design on the Base of the Rhombus Method
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UDC: 004.415.3
Publication Language: Russian
Stuc. intelekt. 2012; 17(3):178-184
Abstract: The variants of processing of n/2 ms bits by design rapid multipliers nxn on the base of adders of the rhombus type are considered. These are: using of improved condition transfer and extension in 1.5 once of digit length of the three-operand adder for account of inclusion ms bits in this length. Best decision is determined by digit length n of the factors.
Keywords: rapid multipliers, rhombus of bit, decomposition, adder by rhombus type, three-operand adder, devolution adder, conditional transfer.
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